Instruction/ maintenance manual of the product CY7C63513C Cypress
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Low-S peed High I/O, 1.5-Mbp s USB Controlle r CY7C63413C CY7C63513C CY7C63613C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-08027 Rev .
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 2 of 32 The sink current for each DAC I/O pin can be individu ally programmed to one of sixteen values using de dicated Isink registers. DAC bits [1:0] can be used as high current outputs with a programmable sink cu rrent range of 3.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 3 of 32 . Note: 1. CY7C63613C is not bonded out for all GPIO pins shown in Logic Bl ock Diagram. Refer to pin confi guration diagram for bon ded ou t pins. See note on p age 12 for firmware code need ed fo r unused GPIO pins.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 4 of 32 Programming Model 14-bit Program Counter (PC) The 14-bit Program Counter (PC) allows access for up to 8 kilobytes of EPROM using the CY7C63413C/513C/613C architecture.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 5 of 32 During an interrupt acknowledge, interrupts are disabled and the 14-bit program counte r , carry flag, and zero flag are wri tten as two bytes of dat a memory . The first byt e is stored i n the memory addressed by the program stack pointer , then the PSP is incremented.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 6 of 32 Instruction Set Summary MNEMONIC operand opcode cycles MNEMONIC operand o pcode cycles HAL T 00 7 NOP 20 4 ADD A,expr data 0.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 7 of 32 Memory Organization Program Memory Organizati on after reset Address 14-bit PC 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128- µ s timer interrupt vector 0x0006 1.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 8 of 32 Dat a Memory Organization The CY7C63413C/513C/6 13C microcontrollers provide 256 bytes of data RAM.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 9 of 32 I/O Register Summary I/O registers are accessed via the I/O Read (IOR D) and I/O Write (IOWR, IOWX) instr uct ions. IORD reads the selected port into the accumula tor . IOWR writes data from the accumu- lator to the selected port.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 10 of 32 Clocking The XT AL IN and XT AL OUT are the clock pin s to the microcon- troller .
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 1 1 of 32 initialization noted under “Reset,” bit 6 of the Processor St atus and Control Register is set to “1” to indicate to the firmware that a W atch Dog Reset occurred. The Watch Dog T imer is a 2-bit timer clocked by a 4.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 12 of 32 Port 3 has eight GPIO pins. Port 3 (8 bits) can be configured as inputs with internal pull-ups, open drain outputs, or tradi- tional CMOS outputs. An open drain output is also a high- impedance input.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 13 of 32 In “Resistive” mode, a 7-k Ω pull-up resistor is conditionally enabled for all pins of a GPIO port. The resistor is enabled for any pin that has been written as a “1.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 14 of 32 The DAC port provide s the CY7C63513C with 8 prog ram- mable current sink I/O pins. Writing a “1” to a DAC I/O pin disables the output current sink (Isi nk DAC) and drives the I/O pin HIGH through an inte grated 14 Kohm resistor .
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 15 of 32 USB Serial Interface Engine (SIE) The SIE allows the microcontroller to communicate with the USB host.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 16 of 32 The Bus Activity bit is a “sticky” bit that indicates if any non-idle USB event has occurred on the USB bu s. The user firmware should check and clear this bit periodically to detect any loss of bus activity .
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 17 of 32 The ‘Acknowledge’ bit is set whenever the SIE engages in a transaction that complete s with an ‘ACK’ packet.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 18 of 32 12-bit Free-running T imer The 12-bit timer p rovides two interru pts (128 µ s and 1.024 ms) and allows the firmware to directly time events that are up to 4 ms in duration.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 19 of 32 The “Single S tep” (bit 1) is provided to support a hardware debugger . Whe n single step is set, the pro cessor will execute one instruction and halt (clear the run bit).
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 20 of 32 Interrupt V ector s The Interrupt V ectors supported by the USB Control ler are listed in T able 27 .
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 21 of 32 T ruth T ables The ‘In’ column repre sents the SIE’s response to the token type. A disabled endpoint will rema in such until firmware chang es it, and all endpoints reset to disabled.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 22 of 32 The response of the SIE can be summarized as follows: 1. the SIE will only respond to valid transactions, and will ig- nore non-valid ones; 2. the SIE will generate IRQ when a val id transaction is completed or when the DMA buffer is corrupted 3.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 23 of 32 T able 29.Details of Modes for Differing T raffic Conditions End Point Mode PID S et End Point Mode 3 2 1 0 token count buf.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 24 of 32 End Point Mode PID S et End Point Mode 3 2 1 0 token count buffer dval DTOG DV AL COUNT Setup In Out ACK 3 2 1 0 response i.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 25 of 32 Absolute Maximum Ratings S torage T emperature ............. .............. .............. .............. .............. ... .............. .............. ....... ...........
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 26 of 32 Notes: 9. Per T able 7-7 of revision 1.1 of USB specification, for C LOAD of 50–600 pF . 10. Measured as largest step size vs. nominal accord ing to measured full scale and zero programmed values.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 27 of 32 . Figure 8. Clock Timing CLOCK t CYC t CL t CH Figure 9. USB Data Signal Timing Figure 10.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 28 of 32 Figure 1 1. Differential to EOP T ransition Skew and EOP Width Figure 12. Differential Dat a Jitter T PERIOD Differential Data Lines Cr osso ver Point Cro sso ve r Po i n t Extended Source EOP Width : T EOPT Receiv er EOP W i dth: T EO PR1 , T EOPR2 Diff.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 29 of 32 Die Pad Locations T able 30.DIe Pad Locations (in microns) Pad # Pin Name X Y Pad # Pin Name X Y 1 D+ 1496.95 2995.0 0 48 V CC 1619.65 3023.60 2 D- 467.40 299 5.00 47 V SS 1719.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 30 of 32 Package Diagrams 48-Lead Shrunk Small Outlin e Package SP48 51-85061-*C 51-85019-* A 40-Lead (600-Mil) Mo lded DIP P2 [+] F.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 31 of 32 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t ained herei n is su bj ect to ch an ge wi t hou t n oti ce.
CY7C63413C CY7C63513C CY7C63613C Document #: 38-08027 Rev . *B Page 32 of 32 Document History Page Document Title: CY7C63413C, CY7C63513C, CY7C63613C Low-speed High I/O, 1.5 -Mbps USB Controller Document Number: 38 -08027 REV . ECN NO. Issue Date Orig.
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