Instruction/ maintenance manual of the product CY7C1527KV18 Cypress
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72-Mbit DDR-II SRAM 2-W ord Burst Architecture CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1 709 • 408-943-2600 Document Number: 001-00437 Rev .
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 2 of 30 Logic Block Diagram (CY7C1516KV18) Logic Block Diagram (CY7C1527KV18) Wri te Reg Wri te Reg CLK A (21:0) Gen. K K Control Logic Address Register Read Add.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 3 of 30 Logic Block Diagram (CY7C1518KV18) Logic Block Diagram (CY7C1520KV18) Wri te Reg Writ e Reg CLK A (21:0) Gen. K K Control Logic Address Register Read Add.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 4 of 30 Pin Configuration The pin configurations for CY7C1516KV18, CY7C 1527 KV18, CY7C1518KV18, and CY7C1520KV18 fo llow . [1] 165-Ball FBGA (13 x 15 x 1 .
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 5 of 30 CY7C1518KV18 (4M x 18) 123456789 10 11 A CQ AA R / W BWS 1 K NC/14 4M LD AA C Q B NC DQ9 NC A NC/.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 6 of 30 Pin Definitions Pin Name I/O Pin Description DQ [x:0] Input Output- Synchronous Dat a Input Outp ut Signals . Inputs are sampled on the rising edge of K and K clocks during valid write operations.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 7 of 30 CQ Output Clock CQ Referenced with Respect to C . This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 8 of 30 Functional Overview The CY7C1516KV18, CY7C1527KV18, CY7C1518 KV18, and CY7C1520KV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and a half cycles when DOFF pi n is tied HIGH.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 9 of 30 Programmable Impedan ce An external resistor , RQ, must be connected between the Z Q pin on the SRAM and V SS to allow the SRAM to adjust its output driver impedance.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 10 of 30 T ruth T able The truth table for the CY7C1516KV18, CY7C1527KV1 8, CY7C1518KV18, and CY7C1520KV18 follow .
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 1 1 of 30 Write Cycle Descriptions The write cycle description tabl e for CY7C1527KV18 follows. [2, 8] BWS 0 K K L L–H – During the data portion of a write sequence, th e single byte (D [8:0] ) is written into the device.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 12 of 30 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 13 of 30 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 14 of 30 T AP Controller St ate Diag ram The state diagram for the T AP controller follows.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 15 of 30 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 16 of 30 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Ma.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 17 of 30 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1516KV18 CY7C1527KV18 CY7 C1518KV18 CY7C1520KV18 Revision Numb er (31:29) 000 000 000 000 V ersion numbe r .
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 18 of 30 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 8.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 19 of 30 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialize d in a predefined manner to prevent unde fined operation s.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 20 of 30 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature .
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 21 of 30 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 370 m.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 22 of 30 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 23 of 30 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consorti um Parame.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 24 of 30 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 25 of 30 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 6, 27, 28] READ READ READ NOP NOP.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 26 of 30 Ordering Information The following table lists all possible speed, package, and temperat ure range options supported for these devi ces. Note that som e options listed may not be availabl e for order entry .
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 27 of 30 250 CY7C1516KV18-250BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm ) Commercial CY7C1527KV18-250BZC CY7C1518KV18-250BZC CY7C1520KV18-250BZC CY7C1516KV18-250BZXC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 28 of 30 167 CY7C1516KV18-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm ) Commercial CY7C1527KV18-167BZC CY7C1518KV18-167BZC CY7C1520KV18-167BZC CY7C1516KV18-167BZXC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.
CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev . *E Page 29 of 30 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.
Document Number: 001-00437 Rev . *E Revised March 30, 2009 Page 30 of 30 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. Al l pr oduct an d company nam es mentione d in this docum ent are the tr ademark s of their re specti ve holders .
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