Instruction/ maintenance manual of the product CY7C1516AV18 Cypress
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72-Mbit DDR-II SRAM 2-W ord Burst Architecture CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-06982 Rev .
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 2 of 30 Logic Block Diagram (CY7C1516A V18) Logic Block Diagram (CY7C1527A V18) Wri te Reg Wri te Reg CLK A (21:0) Gen. K K Control Logic Address Register Read Add.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 3 of 30 Logic Block Diagram (CY7C1518A V18) Logic Block Diagram (CY7C1520A V18) Wri te Reg Writ e Reg CLK A (21:0) Gen. K K Control Logic Address Register Read Add.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 4 of 30 Pin Configuration The pin configuration for CY7C1516A V18, CY7C1527 A V18, CY7C1518A V18, and CY7C1 520A V18 follow . [1] 165-Ball FBGA (15 x 17 x 1 .
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 5 of 30 CY7C1518A V18 (4M x 18) 123456789 10 11 A CQ AA R / W BWS 1 K NC/14 4M LD AA C Q B NC DQ9 NC .
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 6 of 30 Pin Definitions Pin Name IO Pin Descripti on DQ [x:0] Input Output- Synchronous Dat a Input Output S ignals . Inputs are sampled on the rising edge of K and K clocks during valid write operations.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 7 of 30 CQ Output Clock CQ Referenced with Respect to C . This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 8 of 30 Functional Overview The CY7C1516A V18, CY7C152 7A V18, CY7C1518A V18, and CY7C1520A V18 are s.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 9 of 30 current data. The SRAM does this by bypassing the memory array and readin g th e da t a from the registe rs. Depth Expansion Depth expansion requires replicating the LD control signal for each bank.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 10 of 30 T ruth T able The truth table for the CY7C1516A V18, CY7C1527A V18, CY7C1518 A V18, and CY7C1 520A V18 follow .
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 1 1 of 30 Write Cycle Descriptions The write cycle description tabl e for CY7C1527A V18 follows. [2, 8] BWS 0 K K L L–H – During the Data portion of a write sequence, the single byte (D [8:0] ) is written int o the de vi ce .
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 12 of 30 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 13 of 30 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 14 of 30 T AP Controller St ate Diag ram The state diagram for the T AP controller follows.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 15 of 30 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 16 of 30 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Mi.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 17 of 30 Identification R egi ster Definitions Instruction Field Va l u e De scription CY7C1516A V18 CY7C1527A V1 8 CY7C1518A V18 CY7C1520A V18 Revision Numb er (31:29) 000 000 000 000 V ersion number .
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 18 of 30 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 .
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 19 of 30 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operations.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 20 of 30 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature .
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 21 of 30 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200MHz (x8) 70.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 22 of 30 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 23 of 30 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Pa.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 24 of 30 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 25 of 30 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 7, 28, 29 ] READ READ READ NO.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 26 of 30 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 27 of 30 250 CY7C1516A V18-250BZC 51-85195 1 65-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 28 of 30 167 CY7C1516A V18-167BZC 51-85195 1 65-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.
CY7C1516A V18, CY7C1527A V18 CY7C1518A V18, CY7C1520A V18 Document Number: 001-06982 Rev . *D Page 29 of 30 Package Diagram Figure 6. 165-Ball FBGA (15 x 17 x 1.
Document Number: 001-06982 Rev . *D Revised June 16, 2008 Page 30 of 30 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. All pr oduct and co mpany names mentioned i n this documen t are the tr ad emarks of their respe ctive hold ers.
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