Instruction/ maintenance manual of the product CY7C1412AV18 Cypress
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36-Mbit QDR™-II SRAM 2-W ord Burst Architecture CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05615 Rev .
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 2 of 29 Logic Block Diagram (CY7C1410A V18) Logic Block Diagram (CY7C1425A V18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 3 of 29 Logic Block Diagram (CY7C1412A V18) Logic Block Diagram (CY7C1414A V18) 1M x 18 Array CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 4 of 29 Pin Configuration The pin configuration for CY7C1410A V18, CY7C1425 A V18, CY7C141 2A V18, and CY7C1414A V18 fo llow . [1] 165-Ball FBGA (15 x 17 x 1 .
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 5 of 29 CY7C1412A V18 (2M x 18) 123456789 10 11 A CQ NC/144M A WPS BWS 1 K NC/288M RPS A NC/72M CQ B NC Q9 .
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 6 of 29 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during val id write opera tions.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 7 of 29 CQ Echo Clock CQ Referenced with Respect to C . This is a free - running clock and is synchronized to the Input clock for output data (C) of the QDR-II.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 8 of 29 Functional Overview The CY7C1410A V18, CY7C1425A V18, CY7C1412A V18, an d CY7C1414A V18 are synchronous pipelined Burst SRAMs with a read port and a write port.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 9 of 29 Programmable Impedan ce An external resistor , RQ, must be connected between the ZQ pin on the SRAM and V SS to allow the SRAM to adjust its output driver impedance.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 10 of 29 T ruth T able The truth table for CY7C1410A V18, CY7C1425A V18 , CY7C1412A V18, and CY7C1 414A V18 follows. [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write Cycle: Load address on the rising ed ge of K ; input write data on K and K rising edges.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 1 1 of 29 Write Cycle Descriptions The write cycle description tabl e for CY7C1425A V18 follows. [2, 8] BWS 0 K K Comments L L–H – During the Data portion of a write sequence, the single byte (D [8:0] ) is writ te n in to the device.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 12 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 13 of 29 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 14 of 29 T AP Controller St ate Diagram The state diagram for the T AP controller follows.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 15 of 29 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 16 of 29 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max .
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 17 of 29 Identification R egi ster Definitions Instruction Field Va l u e Descrip tion CY7C1410A V18 CY7C1425A V18 CY7C1412 A V18 CY7C1414A V18 Revision Numb er (31:29) 000 000 000 000 V ersion number .
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 18 of 29 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 19 of 29 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operation s. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (All other inputs can be HIGH or LOW).
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 20 of 29 Maximum Ratings Exceeding maximum ratings may im pair the useful life of the device. These user guidelines are not tested. S torage T emperature ....
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 21 of 29 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V I.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 22 of 29 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Condition s Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 23 of 29 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Paramete.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 24 of 29 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 6, 27, 28 ] K 1 2 34 5 8 10 6 7 K R.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 25 of 29 Ordering Information Not all of the speed, package and temperature range s are ava ilable. Please contact your local sales representative or visit www .
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 26 of 29 167 CY7C1410A V18-167BZC 5 1-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1425A V18-167BZC CY7C1412A V18-167BZC CY7C1414A V18-167BZC CY7C1410A V18-167BZXC 51-851 95 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 27 of 29 Package Diagram Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85195 A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.
CY7C1410A V18, CY7C1425A V18 CY7C1412A V18, CY7C1414A V18 Document #: 38-05615 Rev . *E Page 28 of 29 Document History Page Document Title: CY7C1410A V18/CY7C1425A V18/CY7C1412A V1 8/CY7C1414A V18, 36-Mbit QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05615 REV .
Document #: 38-05615 Rev . *E Revised June 13, 2008 Page 29 of 29 QDR RAMs and Qua d Data Ra te RA Ms comprise a ne w fam i ly of pr od uct s developed by Cypress, Hit a chi, IDT , NEC, and Samsung. A l l p r oduct and company names mentioned in this d ocume nt a re the tradem arks of their respective holders.
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