Instruction/ maintenance manual of the product CY7C1393CV18 Cypress
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18-Mbit DDR-II SIO SRAM 2-W ord Burst Architecture CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-07162 Rev .
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 2 of 30 Logic Block Diagram (CY7C1392CV18) Logic Block Diagram (CY7C1992CV18) 1M x 8 Array CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 3 of 30 Logic Block Diagram (CY7C1393CV18) Logic Block Diagram (CY7C1394CV18) 512K x 18 Array CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 4 of 30 Pin Configuration The Pin Configuration for CY7C1392CV1 8, CY7C199 2CV18, CY7C1393CV1 8, and CY7C1394CV18 follows .
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 5 of 30 CY7C1393CV18 (1M x 18) 123456789 10 11 A CQ NC/144M NC/36M R/W BWS 1 K NC/28 8M LD A NC/72M CQ B NC Q9.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 6 of 30 Pin Definitions Pin Name IO Pin Descripti on D [x:0] Input- Synchronous Data input signals. Sampled o n the rising edge of K and K clocks during valid write operations.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 7 of 30 CQ Echo Clock CQ is referenced with r espect to C . This is a free-running clock and is syn chronized to the input clock for output data (C) of the DDR-II.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 8 of 30 Functional Overview The CY7C1392CV18, CY7C1992CV18, CY7C1 393CV18, and CY7C1394CV18 are synchronous pi.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 9 of 30 synchronized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K and CQ is g enerated with respect to K . The timing for the echo clocks is shown in Switching Characteristics on page 23.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 10 of 30 T ruth T able The truth table for CY7C1392CV18, CY7C1992CV1 8, CY7C1393C V18, and CY7C1394CV18 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W DQ DQ Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 1 1 of 30 Write Cycle Descriptions The write cycle description t able for CY7C1 992CV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the data portion of a write sequence, the single b yte (D [8:0] ) is written into the device.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 12 of 30 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 13 of 30 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 14 of 30 T AP Controller St ate Diagram The state diagram for the T AP controller follows.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 15 of 30 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 16 of 30 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Uni.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 17 of 30 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1392CV18 CY7C1992CV18 CY7 C1393CV18 CY7C1394CV18 Revision Numb er (31:29) 000 000 000 000 V ersion number .
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 18 of 30 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 84 2J .
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 19 of 30 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW).
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 20 of 30 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature .....
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 21 of 30 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 575 mA (x9.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 22 of 30 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Condit ions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 23 of 30 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parameter D.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 24 of 30 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 25 of 30 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 7, 28, 29 ] K 123 4 5 6 7 8 K LD R/W A.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 26 of 30 Ordering Information Not all of the speed, package, and temper ature ranges are available. Please cont act your local sale s representative or visit www .
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 27 of 30 250 CY7C1392CV18-250BZ C 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1992CV18-250BZC CY7C1393CV18-250BZC CY7C1394CV18-250BZC CY7C1392CV18-250BZXC 5 1-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 28 of 30 167 CY7C1392CV18-167BZ C 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1992CV18-167BZC CY7C1393CV18-167BZC CY7C1394CV18-167BZC CY7C1392CV18-167BZXC 5 1-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Document #: 001-07162 Rev . *C Page 29 of 30 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.
Document #: 001-07162 Rev . *C Revised May 22, 2008 Page 30 of 30 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s developed by Cypress, I DT , NEC, R enesas, and Sa msung. All pr oduct and comp any names mentioned i n this documen t are the tr ad emarks of their respe ctive hold ers.
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If you already are a holder of Cypress CY7C1393CV18, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Cypress CY7C1393CV18.
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