Instruction/ maintenance manual of the product CY7C1386DV25 Cypress
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18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Cypress Semic onductor Corpora tion • 198 Cham pion Cour t • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-05548 Rev .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 2 of 30 Logic Block Diagram – CY7C1386DV25 /CY7C1386FV25 [3 ] (512K x 36) Logic Block Diagram – CY7C13.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 3 of 30 Pin Configurations A A A A A 1 A 0 NC/72M NC/36M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 4 of 30 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 5 of 30 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1386DV25 (512K x 36) 234 5.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 6 of 30 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to selec t one of the a ddress locations .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 7 of 30 Functional Overview All synchronous inpu ts pass through input registers controlled by the rising edge of th e clock. All data outputs pass through output registers controlled by th e rising edge of the clock.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 8 of 30 The write signals (GW , BWE , and BW X ) and ADV inputs are ignored during this first cycl e. ADSP triggered write accesses require two cl ock cycles to complete.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 9 of 30 ZZ Mode Electrical Characteristics Parameter Description T est Conditions Min. Max. Unit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 80 mA t ZZS Device operation to ZZ ZZ > V DD – 0.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 10 of 30 Partial T r uth T able for Read/W rite [5, 10] Function (CY7C1386DV25/CY7C 1386FV25) GW BWE BW D .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 1 1 of 30 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1386DV25/CY7C 1387DV25/CY7C13 86FV25/ CY7C1387FV25 incorporates a serial boundary scan test access port (T AP).
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 12 of 30 Instruction Register Three-bit instructions can be serially loaded into the instructio n register . This register is loade d when it is placed between the TDI and TDO balls as show n in the T AP Controller Block Diagram .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 13 of 30 The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required; that is, w hile data captured is shifted out, the preloa ded data can be shifted in.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 14 of 30 T AP AC T est Conditions Input pulse levels ................... ........... .............. .....V SS to 2.5V Input rise and fall time ..............
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 15 of 30 Identification Register Definitions Instruction Field CY7C1386DV25/ CY7C1386FV2 5 CY7C1387DV25/ CY7C1387FV25 Description Revision Number (31:29) 000 000 Describes the version number .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 16 of 30 1 19-Ball BGA Boundary Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball I.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 17 of 30 165-Ball BGA Boundary Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1N 6 3 1 D 1 .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 18 of 30 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guideline s, not tested. S torage T emperature ....
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 19 of 30 Cap acit ance [19] Parameter D escription T est Conditions 100 TQFP Package 11 9 B G A Package 165 FBGA Package Unit C IN Input Capacit a nce T A = 25 ° C, f = 1 MHz, V DD /V DDQ = 2.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 20 of 30 Switching Characteristics Over the Operating Range [20, 21] Parameter Descriptio n 250 MHz 200 MHz 167 MHz Unit Min. Max. Min. Max. Min. Max. t POWER V DD (T ypical) to the first Access [22] 1 11 ms Clock t CYC Clock Cycle Time 4.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 21 of 30 Switching W aveforms Read Cycle Timing [26] t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 22 of 30 Write Cycle T iming [26, 27] Switching W aveforms (continued ) t CYC t CL CLK ADSP t ADH t ADS AD.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 23 of 30 Read/Write Cycle Timing [26, 28, 29] Switching W aveforms (continued ) t CYC t CL CLK ADSP t ADH .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 24 of 30 ZZ Mode T iming [30, 31] Switching W aveforms (continued ) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 30.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 25 of 30 Ordering Information Not all of the speed, package, and temperature ranges are av ailable. Pl ease contact your local sales representative or visit www .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 26 of 30 250 CY7C1386DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (1 4 x 20 x 1.4 mm) Pb-Free Commercial CY7C1387DV25-250AXC CY7C1386FV25-250BGC 5 1-851 15 1 19-ball Ball Grid Array (14 x 22 x 2.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 27 of 30 Package Diagrams Figure 1. 100-Pin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 28 of 30 Figure 2. 1 19-Ball BGA (14 x 22 x 2.4 mm) (51-851 15) Package Diagrams (continued) 51-851 15-*B .
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . * E Page 29 of 30 © Cypress Semicond uctor Corporation , 2006-2007.
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 30 of 30 Document History Page Document Title: CY7C1386DV25/CY7C1 387D V25/CY7C1386FV25/ CY7C1387F V25 18-M bit (512K x 36/1M x 18) Pipelined DCD Sync SRAM Document Number: 38-05548 REV .
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