Instruction/ maintenance manual of the product CY7C1380C Cypress
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18-Mb (512K x 36/1M x 18) Pipelined SRAM CY7C1380C CY7C1382C Cypress Semiconductor Corpora tion • 3901 North First S treet • San Jose , CA 95134 • 408-943-26 00 Document #: 38-05237 Rev .
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 2 of 36 1 2 Logic Block Diagram – CY7C1380C (512K x 36) ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BWE GW CE 1 C.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 3 of 36 Pin Configurations A A A A A 1 A 0 NC / 72M NC / 36M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DD.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 4 of 36 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC NC DQP C DQ C DQ D DQ C DQ D AA A A ADSP V DDQ AA DQ.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 5 of 36 Pin Configurations (continued) 165-ball fBGA CY7C1380C (512K x 36) 23 4 567 1 A B C D E F G H J K L M N P R TDO NC / 288M NC DQP C DQ C D.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 6 of 36 CY7C1380C–Pin Definitions Name TQFP BGA fBGA I/O Description A 0 , A 1 , A 37,36,32 , 33,34,35, 42,43,44,45, 46,47,48, 49,50,81, 82,99,.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 7 of 36 ADSP 84 A4 B9 Input- Synchronous Address Strobe from Proc ess or , sample d on the rising edge of CLK, active LOW . W hen asserted LOW , addresses presented to the device are captured in the address registers.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 8 of 36 V SSQ 5,10,21,26,55, 60,71, 76 - - I/O Ground Ground for t he I/O circ uitry . V DDQ 4,1 1,20,27,54, 61,70, 77 A1,F1,J1,M1, U1, A7,F7,J7,M7, U7 C3,C9,D3,D9, E3,E9,F3,F9,G 3, G9,J3,J9, K3,K9,L3, L9,M3,M9,N3, N9 I/O Power Supply Power supply for the I/O ci rcuitry .
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 9 of 36 CY7C1382C:Pin Definitions Name TQFP BGA fBGA I/O Description A 0 , A 1 , A 37,36,32, 33,34,35, 42,43,44, 45,46,47, 48,49,50, 80,81,82, 99.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 10 of 36 ADSP 84 A4 B9 Input- Synchronous Address Strobe from Process or , sampled on the rising edge of CLK, active LOW . When asserted LOW , addresses presented to the device are captured in the address registers.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 1 1 of 36 V DDQ 4,1 1,20,27,54, 61,70, 77 A1,A7,F1,F7, J1,J7,M1,M7, U1,U7 C3,C9,D3,D9, E3,E9, F3,F9,G3 , G9,J3,J9, K3,K9,L3, L9,M3,M9,N3, N9 I/O Power Sup- ply Power supply for the I/O circu itry .
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 12 of 36 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 13 of 36 Asserting ADV LOW at clock rise will automatically increment the burst counter to the next ad dress in the burst sequence. Both Read and Write burst operatio ns are supported. Sleep Mode The ZZ input pin is an asynchronous input.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 14 of 36 READ Cycle, Continue Burst Next H X X L X H L H H L-H T ri -S tate WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle,.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 15 of 36 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1380C incorporates a seri al boundary scan test access port (T AP). This port ope rates in accordance with IEEE S tandard 1 149.1-1990 but do es not have the set of functions required for full 1 149.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 16 of 36 TDI and TDO ba lls as show n in the T ap Contro ller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE in struction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in th e pre v i o us section.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 17 of 36 Note that since the PRELOAD part of the command is not implemented, putting the T AP to the Update-DR state while performing a SAMPLE/PRELOAD instruction w ill have the same effect as the Pause-DR command.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 18 of 36 3.3V T AP AC T est Conditions Input pulse levels ........ . .............. .............. ...........V SS to 3.3V Input rise and fall times ........... ......... .. ............ .........
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 19 of 36 Identification Register Definitions INSTRUCTION FIELD CY7C1380C (512KX36) CY7C1382C (1MX18) DESCRIPTION Revision Number (31:29) 010 0100 Describes the version number .
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 20 of 36 1 19-Ball BGA Boundary Scan Order CY7C1380C (512K x 36) BIT# BALL ID BIT# BALL ID 1 K4 37 B2 2 H4 38 P4 3M 4 3 9 N 4 4F 4 4 0 R 6 5B 4 4.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 21 of 36 CY7C1382C (1M x 18) BIT# BALL ID BIT# BALL ID 1 K4 37 B2 2 H4 38 P4 3M 4 3 9 N 4 4F 4 4 0 R 6 5B 4 4 1 T 5 6A 4 4 2 T 3 7G 4 4 3 R 2 8C .
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 22 of 36 165-Ball fBGA Boundary Scan Order CY7C1380C (512K x 36) BIT# BALL ID BIT# BALL ID 1B 6 3 7 N 6 2B 7 3 8 R 6 3A 7 3 9 P 6 4B 8 4 0 R 4 5A.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 23 of 36 CY7C1382C (1M x 18) BIT# BALL ID BIT# BALL ID 0B 6 3 6 N 6 1B 7 3 7 R 6 2A 7 3 8 P 6 3B 8 3 9 R 4 4A 8 4 0 R 3 5B 9 4 1 P 4 6A 9 4 2 P 3.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 24 of 36 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ......................... .. ... ... –65 ° C to +150 ° C Ambient T emp erature with Power Applied .
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 25 of 36 I SB3 Automatic CE Power-down Current—CMOS Inputs V DD = M ax, Device Deselected, or V IN ≤ 0.3V o r V IN > V DDQ – 0.3V f = f MAX = 1/t CYC 4.0-ns cycle, 250 MHz 105 mA 4.4-ns cycle, 225 MHz 100 mA 5.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 26 of 36 AC T est Loads and W aveforms OUTPUT R = 317 Ω R = 351 Ω 5p F INCLUDING JIG AND SCOPE (a) (b) OUTPUT R L = 50 Ω Z 0 = 50 Ω V L = 1.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 27 of 36 Switching Characteristics Over the Operating Range [19, 20] Parameter Description 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Un it Min. Max Min. Max Min. Max t POWER V DD (T ypical) to the first Access [15] 1 1111 ms Clock t CYC Clock Cycle T ime 4.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 28 of 36 Switching W aveforms Read Cycle Timing [21] Notes: 21. On this diagram, when CE is L OW: CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 29 of 36 Write Cycle T iming [21, 22] Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 30 of 36 Read/Write Cycle Timing [21, 23, 24 ] Note: 23. The data bus (Q) remain s in high-Z following a WRIT E cycl e, unless a new read access is initiated by ADSP or ADSC .
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 31 of 36 Notes: 25. Device must be deselected when ente ring ZZ mode. See Cycle Descr iptions t ab le for all possible signal conditi ons to deselect the device.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 32 of 36 Ordering Information Speed (MHz) Ordering Code Pa ckage Name Part and Package T ype Operating Range 250 CY7C1380C-250AC CY7C1382C-250AC A101 100-lead Thin Qu ad Flat Pack (14 x 20 x 1.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 33 of 36 © Cypress Semico nductor Corpor ation, 2004. Th e information cont ained herein is subject to chan ge without noti ce. Cypress Semico nductor Corporation assumes no resp onsibility for the use of any circ uitry other than cir cuitry embodied i n a Cypress Semi conductor product.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 34 of 36 Package Diagrams (continued) 51-851 15-*B 1 1 9-Lead PBGA (14 x 22 x 2.4 mm) BG1 19 [+] Feedback.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 35 of 36 Package Diagrams (continued) i486 is a trademark, and Intel and Pentium are registered trade marks of Intel Corporation. Po werPC is a trademark of IBM Corporation. All pro duct and company names mentioned in this document are the trademarks of their respective holder s.
CY7C1380C CY7C1382C Document #: 38-05237 Rev . *D Page 36 of 36 Document History Page Document Title: CY7C1380C/CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05237 REV .
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