Instruction/ maintenance manual of the product CY7C138 Cypress
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CY7C138, CY7C139 4K x 8/9 Dual-Port S t atic RAM with Sem, Int, Busy Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06037 Rev .
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 2 of 17 Pin Configurations Figure 1. 68-Pin PLCC (T op View) T able 1. Pin Definitions Left Port Right Port Description I/O 0L–7L(8L) I/O 0R–7R.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 3 of 17 Maximum Ratin gs Exceeding maximum ratings may impair the useful life of the device. These user guid elines are not tested. [5] S torage T emperature ................ .............. ... –65 ° C to +150 ° C Ambient T emperature with Power Applied .
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 4 of 17 Electrical Characteristics Over the Operating Range (continued) Parameter Descriptio n T est Conditions 7C138-35 7C139-35 7C138-55 7C139-55 Unit Min Max Min Max V OH Output HIGH V oltage V CC = Min.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 5 of 17 Figure 2. AC T est Loads and Waveforms 3.0V GND 90% 90% 10% < 3n s < 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load 1) R1 = 893 Ω 5V OUTPUT R2 = 347 Ω C= 3 0 pF R TH = 250 Ω V TH = 1.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 6 of 17 t HD Data Hold From W rite End 0 0 0 0 ns t HZWE [1 1,12] R/W LOW to High Z 10 15 20 25 ns t LZWE [1 1,12] R/W HIG H to Low Z 3 3 3 3 ns t W.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 7 of 17 Figure 5. Read Ti ming with Port-to-P ort Delay (M/S = L) [20, 21] Figure 6. Write Cycle No.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 8 of 17 Figure 7. W rite Cy cle No. 2: R/W Three-S tates Dat a I/Os (Either Port) [22, 24, 25] Figure 8.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 9 of 17 Figure 9. Timing Diagra m of Sema phore Contention [27, 28, 29] Figure 10. T iming Diagram of Read with BUSY (M /S = HIGH) [21] Switching W .
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 10 of 17 Figure 1 1. Write T iming with Busy Input (M/S =LOW) Notes 27. I/O 0R = I/O 0L = LOW (request semaphore); CE R = CE L = HIGH 28. Semaphores are reset (available to both ports) at cycle start.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 1 1 of 17 Figure 13. B usy Timing Diagram No. 2 (Address Arbitration ) [30] Note 30. If t PS is violated, the busy signal wil l be asserted on one side or the oth er , but there is no guarantee on which side BUSY will be asserted.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 12 of 17 Figure 14. Interrupt Timing Diagrams Notes 31. t HA depends on which enable pin (CE L or R/W L ) is deasserte d first. 32. t INS or t INR depends on which enable pin (CE L or R/W L ) is assert ed last.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 13 of 17 Architecture The CY7C138/9 consists of an array of 4K words of 8/9 bits each of dual-port RAM cell s, I/O and address lines, and co ntrol signals (CE , OE , R/W ). These control pins permit indep endent access for reads or writes to any location in memory .
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 14 of 17 T able 3. Non-Cont ending Read /Write Input s Outputs Operation CE R/W OE SEM I/O 0-7/8 H X X H High Z Power-Down H H L L Data Out Read Dat.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 15 of 17 Figure 15. T ypical DC and AC Characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 –55 25 125 1.2 1.0 120 80 0 1.0 2.0 3.0 4.0 OUTPUT SOURCE CURRENT (mA) SUPPL Y VOL T AGE (V) NORMALIZED SUPPL Y CURRENT vs.
CY7C138, CY7C139 Document #: 38-06037 Rev . *D Page 16 of 17 Ordering Information 4K x8 Dual-Port SRAM Spee d (ns) Ordering Code Package Name Package T ype Operating Range 15 CY7C138-15JC J81 68-Lea d.
Document #: 38-06037 Rev . *D Revised March 12, 2009 Page 17 of 17 All product s and company names ment ioned in thi s document may be the tra demarks of thei r respective h olders. CY7C138, CY7C139 © Cypress Semicondu ctor Corporati on, 2005-2009. The information cont ained herein i s subject to change witho ut notice.
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