Instruction/ maintenance manual of the product CY7C1371D Cypress
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18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture CY7C1371D CY7C1373D Cypress Semiconductor Corpora tion • 198 Champion Court • San J ose , CA 95134-1709 • 408-943-2600 Document #: 38-05556 Rev .
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 2 of 29 Logic Block Diagram – CY7C1371D (512 K x 36) Logic Block Diagram – CY7C1373D (1M x 18) C MODE BW A BW B WE CE1 CE2 CE3 OE READ LOGIC .
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 3 of 29 Pin Configurations 100-Pin TQFP Pinout A A A A A1 A0 NC/288M NC/144M V SS V DD NC/36M A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 4 of 29 100-Pin TQFP Pinout Pin Configurations (continued) A A A A A1 A0 NC/288M NC/144M V SS V DD NC/36M A A A A A A A NC NC V DDQ V SS NC DQP A.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 5 of 29 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC/576M NC/1G DQP C DQ C DQ D DQ C DQ D AA A A V DDQ CE.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 6 of 29 Pin Configurations (continued) 165-Ball FBGA Pinout CY7C137 1D (512K x 36) 234 567 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP .
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 7 of 29 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select o ne of the addr ess locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter .
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 8 of 29 Functional Overview The CY7C1371D/CY7 C1373D is a synchronou s flow through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers contro lled by the rising edge of the clock.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 9 of 29 details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled b y BW X signals.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 10 of 29 T ruth T able [2, 3, 4, 5, 6, 7, 8] Operation Address Used CE 1 CE 2 CE 3 ZZ ADV/LD WE BW X OE CEN CLK DQ Deselect Cycle None H X X L L .
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 1 1 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1371D/CY7C1373D incorpora tes a serial boundary scan test access port (T AP).This part is fully compliant wi th 1 149.1. T he T AP operates using JEDEC-standard 3.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 12 of 29 instruction if the controller is placed in a reset state as described in th e previous secti on.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 13 of 29 boundary scan path when multiple devices are connected together on a board. EXTEST Output Bus T ri-St ate IEEE S tandard 1 149.1 mandates tha t the T AP controller be able to put th e output bu s into a tri-st ate mode.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 14 of 29 T AP AC Switching Characteristics Over the Operating Range [10, 1 1] Parameter Description Min Max Unit Clock t TCYC TCK Clock Cycle T i.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 15 of 29 3.3V T AP AC T est Conditions Input pulse levels ...... .............. ............ .............. . .V SS to 3.3V Input rise and fall times ......... .............. ........... .........
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 16 of 29 Identification Register Definitions Instruction Field CY7C1371D (512K X 36) CY7C1373D (1M X 18) Description Revision Number (31:29) 000 .
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 17 of 29 1 19-Ball BGA Boundary Scan Order [13, 14] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball I D 1 H4 23 F6 45 G4 67 L1 2 T 4 2 4E 7 .
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 18 of 29 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N 7 3 2 C 1 1 6 2 D 2 3 N10 33 A1.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 19 of 29 Maximum Ratings Exceeding maximum rati ngs may impair the useful life of the device. These user guid elines are not tested. S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emp erature with Power Applied .
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 20 of 29 Cap acit ance [18] Parameter Description T est Conditions 100 TQFP Package 1 19 BGA Package 165 FBGA Package Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 21 of 29 Switching Characteristics Over the Operating Range [23, 24] Parameter Descriptio n 133 MHz 100 MHz Unit Min Max Min Max t POWER [19] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 2.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 22 of 29 Switching W aveforms Read/Write W avefo rms [25, 26, 27] WR I T E D(A 1) 123456789 CLK t CY C t CL t CH 10 CE t CE H t CE S WE CE N t C .
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 23 of 29 NOP , ST ALL AND DESELECT Cycles [25, 26, 28] Switching W aveforms (continued) READ Q(A3) 456 789 1 0 A3 A4 A5 D(A4) 123 CLK CE WE CEN B.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 24 of 29 ZZ Mode T iming [29, 30] Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZR E C AL L I NP UT S ( e x ce p t ZZ) DO N’T CA R E I DDZ Z t ZZI t RZ Z I Ou t p ut s ( Q) Hig h- Z DES ELEC T or REA D O nly Notes: 29.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 25 of 29 Ordering Information Not all of the speed, package and temper ature ranges are avail able. Please c ontact your local sales representative or visit www . cypress.com for actual products of fered.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 26 of 29 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 27 of 29 Figure 2. 1 19-Ball BGA (14 x 22 x 2.4 mm) (51-851 15) Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 28 of 29 © Cypress Semico nductor Corpor ation, 2004- 2007. The inform ation contai ned herein is sub ject to change wi thout notice. Cypr ess S emiconduct or Corporation a ssumes no responsi bility for the use of any circuitr y other than circui try embodied in a Cy press product.
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 29 of 29 Document History Page Document Title: CY7C1371D/CY7C1373D 18-Mb it (512K x 36/1 Mbit x 18) flow through SRAM with NoBL™ Arc hitecture Document Number: 38-05556 REV . ECN NO. Issue Date Orig.
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