Instruction/ maintenance manual of the product CY7C1352G Cypress
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4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture CY7C1352G Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05514 Rev .
CY7C1352G Document #: 38-05514 Rev . *D Page 2 of 12 Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access T ime 2.6 2.8 3.5 4.0 ns Maximum Operating Current 325 265 240 225 mA Maximum C.
CY7C1352G Document #: 38-05514 Rev . *D Page 3 of 12 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 25 6K address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter .
CY7C1352G Document #: 38-05514 Rev . *D Page 4 of 12 Functional Overview The CY7C1352G is a synchronous-pipelin ed Burst SRAM designed specifically to el iminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock.
CY7C1352G Document #: 38-05514 Rev . *D Page 5 of 12 Interleaved Burst Address T able (MODE = Floating or V DD ) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 0.
CY7C1352G Document #: 38-05514 Rev . *D Page 6 of 12 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ......... ............ ........... ..... − 65°C to +150°C Ambient T emperature with Power Applied .
CY7C1352G Document #: 38-05514 Rev . *D Page 7 of 12 I SB4 Automatic CE Power-down Current—TTL Inputs V DD = Max, Device Deselected, V IN ≥ V IH or V IN ≤ V IL , f = 0 All speeds 45 mA Cap acit ance [1 1] Parameter Description T es t Conditions 100 TQFP Max.
CY7C1352G Document #: 38-05514 Rev . *D Page 8 of 12 Switching Characteristics Over the Operating Range [16, 17] Parameter Description –250 –200 –166 –133 Unit Min. Max. Min. Max. Min. Max. Min. Max. t POWER V DD (typical) to the first Access [12] 11 11 m s Clock t CYC Clock Cycle T ime 4.
CY7C1352G Document #: 38-05514 Rev . *D Page 9 of 12 Switching W aveforms Read/W rite Timing [18, 19, 20] Notes: 18. For this waveform ZZ is tied low . 19. When C E is LOW: CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW . W h en CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH.
CY7C1352G Document #: 38-05514 Rev . *D Page 10 of 12 NOP , ST ALL, and DESELECT Cycles [18, 19, 21] ZZ Mode Timing [22, 23] Notes: 21. The IG NOR E CLO CK EDG E or ST ALL cycle (Clock 3) illustrated CEN being used to create a p a use. A write is not performed duri ng this cycle.
CY7C1352G Document #: 38-05514 Rev . *D Page 1 1 of 12 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C1352G Document #: 38-05514 Rev . *D Page 12 of 12 Document History Page Document Title: CY7C1352G 4-Mbit (256K x 18) Pipe lined SRAM with NoBL™ Arch itecture Document Number: 38-05514 REV .
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