Instruction/ maintenance manual of the product CY7C1350G Cypress
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4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture CY7C1350G Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05524 Rev .
CY7C1350G Document #: 38-05524 Rev . *F Page 2 of 15 Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit Maximum Access T ime 2.6 2.8 3.5 4.0 4.
CY7C1350G Document #: 38-05524 Rev . *F Page 3 of 15 Pin Configurations (continued) 23 4 56 7 1 A B C D E F G H J K L M N P R T U DQ A V DDQ NC/576 M NC/1G DQ C DQ D DQ C DQ D AA AA NC/18M V DDQ CE 2 .
CY7C1350G Document #: 38-05524 Rev . *F Page 4 of 15 Functional Overview The CY7C1350G is a synchronous-pipelin ed Burst SRAM designed specifically to el iminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock.
CY7C1350G Document #: 38-05524 Rev . *F Page 5 of 15 On the subsequent clock rise the data line s are a utomatically tri-stat ed regardless o f the stat e of the OE input signal. This allows the external lo gic to present the data on DQs and DQP [A:D] .
CY7C1350G Document #: 38-05524 Rev . *F Page 6 of 15 NOP/WRITE ABORT (Begin Burs t) None L L L L H X L L-H T ri-S tate WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-S tate IGNORE CLOCK EDGE .
CY7C1350G Document #: 38-05524 Rev . *F Page 7 of 15 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ......... ............ ........... ..... − 65°C to +150°C Ambient T emperature with Power Applied .
CY7C1350G Document #: 38-05524 Rev . *F Page 8 of 15 I SB3 Automatic CE Power-Down Current—CMOS Inputs V DD = Max, Device Deselected, or V IN ≤ 0.3V or V IN > V DDQ – 0.3V f = f MAX = 1/t CYC 4-ns cycle, 250 MHz 105 mA 5-ns cycle, 200 MHz 95 mA 6-ns cycle, 166 MHz 85 mA 7.
CY7C1350G Document #: 38-05524 Rev . *F Page 9 of 15 Switching Characteristics Over the Operating Range [17, 18] –250 –20 0 –166 –133 –100 Parameter Description Min. Max. Min. Max. Mi n. Max. Min. Max. Min. Max. Unit t POWER V DD (typical) to the first Access [13] 1 1 1 1 1 ms Clock t CYC Clock Cycle T ime 4.
CY7C1350G Document #: 38-05524 Rev . *F Page 10 of 15 Switching W aveforms Read/W rite Timing [19, 20, 21] Notes: 19. For this waveform ZZ is tied LOW . 20. When CE is LOW , CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW . When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH.
CY7C1350G Document #: 38-05524 Rev . *F Page 1 1 of 15 NOP , ST ALL, and DESELECT Cycles [19, 20 , 22] ZZ Mode T iming [23, 24] Notes: 22. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrates CEN being used to create a p ause. A write is not performed during this cycle.
CY7C1350G Document #: 38-05524 Rev . *F Page 12 of 15 Ordering Information Not all of the speed, package and temperature ranges are av ailable. Please contact your local sales representative or visit www .
CY7C1350G Document #: 38-05524 Rev . *F Page 13 of 15 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0.
CY7C1350G Document #: 38-05524 Rev . *F Page 14 of 15 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C1350G Document #: 38-05524 Rev . *F Page 15 of 15 Document History Page Document Title: CY7C1350G 4-Mbit (128K x 36) Pipe lined SRAM with NoBL™ Arch itecture Document Number: 38-05524 REV .
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