Instruction/ maintenance manual of the product CY7C1339G Cypress
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4-Mbit (128K x 32) Pipelined Sync SRAM CY7C1339G Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05520 Rev . *F Revised July 5, 2006 Features • Registered inp uts and outputs for pipelined op er ation • 128K × 32 common I/O architectur e • 3.
CY7C1339G Document #: 38-05520 Rev . *F Page 2 of 18 Pin Configurations Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access T ime 2.6 2.
CY7C1339G Document #: 38-05520 Rev . *F Page 3 of 18 Pin Configurations (continued) Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address In puts used to select one of the 128K address loca tions . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active.
CY7C1339G Document #: 38-05520 Rev . *F Page 4 of 18 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.
CY7C1339G Document #: 38-05520 Rev . *F Page 5 of 18 signal. Consecutive single R ead cycles are supported. Once the SRAM is desel ected at clo ck rise by the chip select and either ADSP or ADSC signals, its output will tri-state immedi- ately .
CY7C1339G Document #: 38-05520 Rev . *F Page 6 of 18 T ruth T able [2, 3, 4, 5, 6, 7] Operation Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power-down None H X X L X L X .
CY7C1339G Document #: 38-05520 Rev . *F Page 7 of 18 Partial T ruth T able for Read/W rite [2, 8] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte A – DQ A H L HHH L W.
CY7C1339G Document #: 38-05520 Rev . *F Page 8 of 18 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T e mperature with Power Applied .
CY7C1339G Document #: 38-05520 Rev . *F Page 9 of 18 I SB3 Automatic CE Power-down Current—CMOS Inputs V DD = Max, Device Deselected, or V IN ≤ 0.3V or V IN > V DDQ – 0.3V f = f MAX = 1/t CYC 4-ns cycle, 250 MHz 105 mA 5-ns cycle, 200 MHz 95 mA 6-ns cycle, 166 MHz 85 mA 7.
CY7C1339G Document #: 38-05520 Rev . *F Page 10 of 18 Switching Characteristics Over the Operating Range [12, 13, 14, 15, 16, 17] Parameter Description –250 –200 –166 –133 Unit Min. Max. Min. Max. Min. Max. Min. Max. t POWER V DD (T ypical) to the first Access [12] 11 11 m s Clock t CYC Clock Cycle T ime 4.
CY7C1339G Document #: 38-05520 Rev . *F Page 1 1 of 18 Switching W aveforms Read Cycle Timing [18] Note: 18. On this diagram, when CE is LOW , CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW .
CY7C1339G Document #: 38-05520 Rev . *F Page 12 of 18 Write Cycle T iming [18, 19] Note: 19. Full width write can be initiat ed by either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW .
CY7C1339G Document #: 38-05520 Rev . *F Page 13 of 18 Read/Write Cycle Timing [18, 20, 21 ] Notes: 20. The data bus (Q) remain s in high-Z following a WRIT E cycl e, unless a new read access is initiated by ADSP or ADSC .
CY7C1339G Document #: 38-05520 Rev . *F Page 14 of 18 ZZ Mode T iming [22, 23] Notes: 22. Device must be deselected when ente ring ZZ mode. See Cycle Descr iptions t ab le for all possible signal conditi ons to deselect the device. 23. DQs are in high -Z when exiting ZZ sleep mode.
CY7C1339G Document #: 38-05520 Rev . *F Page 15 of 18 Ordering Information Not all of the speed, package and temperature ranges are a vailable. Please contact your local s ales representative or visit www .
CY7C1339G Document #: 38-05520 Rev . *F Page 16 of 18 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0.
CY7C1339G Document #: 38-05520 Rev . *F Page 17 of 18 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C1339G Document #: 38-05520 Rev . *F Page 18 of 18 Document History Page Document Title: CY7C1339G 4-Mbit (128K x 32) Pipeline d Syn c SRAM Document Number: 38-05520 REV .
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