Instruction/ maintenance manual of the product CY7C1334H Cypress
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2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture CY7C1334H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05678 Rev .
CY7C1334H Document #: 38-05678 Rev . *B Page 2 of 13 . Selection Guide 166 MHz 133 MHz Unit Maximum Access T ime (t CO ) 3.5 4.0 ns Maximum Operating Current (I DD ) 240 225 mA Maximum CMOS S tandby C.
CY7C1334H Document #: 38-05678 Rev . *B Page 3 of 13 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 64K address loca tions . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter .
CY7C1334H Document #: 38-05678 Rev . *B Page 4 of 13 Functional Overview The CY7C1334H is a synchronous-pipeli ned Burst SRAM designed specifically to el iminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock.
CY7C1334H Document #: 38-05678 Rev . *B Page 5 of 13 Interleaved Burst Address T able (MODE = Floating or V DD ) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 0.
CY7C1334H Document #: 38-05678 Rev . *B Page 6 of 13 Write Cycl e Description [2, 3] Function WE BW D BW C BW B BW A Read H X X X X Wri t e − No bytes written L H H H H Wri t e B y t e A − (DQ A ).
CY7C1334H Document #: 38-05678 Rev . *B Page 7 of 13 Maximum Rating (Above which the useful life may be impaired. For user guide- lines not tested.) S torage T emperature ......... ............ ........... ..... − 65°C to +150°C Ambient T emperature with Power Applied .
CY7C1334H Document #: 38-05678 Rev . *B Page 8 of 13 Cap acit ance [1 1] Parameter Description T est Con ditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C , f = 1 MHz, V DD = 3.
CY7C1334H Document #: 38-05678 Rev . *B Page 9 of 13 Switching Characteristics Over the Operating Range [12, 13] 166 MHz 133 MHz Parameter Description Min. Max. Min. Max. Unit t POWER V DD (typical) to the First Access [14] 11 m s Clock t CYC Clock Cycle T ime 6.
CY7C1334H Document #: 38-05678 Rev . *B Page 10 of 13 Switching W aveforms Read/W rite Timing [18, 19, 20] Notes: 18. For this waveform ZZ is tied LOW. 19. When C E is LOW, CE 1 is LOW , C E 2 is HIGH and CE 3 is LOW . When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH.
CY7C1334H Document #: 38-05678 Rev . *B Page 1 1 of 13 NOP , ST ALL, and Des elect Cyc les [18, 19, 21] ZZ Mode Timing [22, 23] Notes: 21. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrated CEN being used to create a p ause. A write is not performed duri ng this cycle.
CY7C1334H Document #: 38-05678 Rev . *B Page 12 of 13 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C1334H Document #: 38-05678 Rev . *B Page 13 of 13 Document History Page Document Title: CY7C1334H 2-Mbit (64K x 32 ) Pipelined SRAM with NoBL™ Architectu re Document Number: 38-05678 REV .
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