Instruction/ maintenance manual of the product CY7C1324H Cypress
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2-Mbit (128K x 18) Flow-Through Sync SRAM CY7C1324H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 001-00208 Rev . *B Revised April 26, 2006 Features • 128K x 18 common I/O • 3.
CY7C1324H Document #: 001-00208 Rev . *B Page 2 of 15 Selection Guide 133 MHz Unit Maximum Access T i me 6.5 ns Maximum Operating Current 225 mA Maximum S tandby Curre nt 40 mA Pin Configurations 100-.
CY7C1324H Document #: 001-00208 Rev . *B Page 3 of 15 Pin Definitions Name I/O Descriptio n A0, A1, A Input- Synchronous Address Inputs used to select one of the 128 K add ress location s. Sampled at the rising edge of the CLK i f ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active.
CY7C1324H Document #: 001-00208 Rev . *B Page 4 of 15 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge o f the clock.
CY7C1324H Document #: 001-00208 Rev . *B Page 5 of 15 ZZ Mode Electrical Characteristics Parameter Description T est Co nd itions Min. Max. Unit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 40 mA t ZZS Device operation to ZZ ZZ > V DD – 0.
CY7C1324H Document #: 001-00208 Rev . *B Page 6 of 15 T ruth T able for Read/Write [2, 3] Function GW BWE BW B BW A Read H H X X Read H L H H Write Byte (A, DQP A )H L H L Write Byte (B, DQP B )H L L .
CY7C1324H Document #: 001-00208 Rev . *B Page 7 of 15 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ................ .............. ... –65 ° C to +150 ° C Ambient T e mperature with Power Applied .
CY7C1324H Document #: 001-00208 Rev . *B Page 8 of 15 Cap acit ance [8] Parameter Description T est Cond itio ns 100 TQFP Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.
CY7C1324H Document #: 001-00208 Rev . *B Page 9 of 15 Switching Characteristics Over the Operating Range [9, 10] Parameter Description -133 Unit Min. Max. t POWER V DD (T ypical) to the First Access [1 1] 1m s Clock t CYC Clock Cycle T ime 7.5 ns t CH Clock HIGH 2.
CY7C1324H Document #: 001-00208 Rev . *B Page 10 of 15 Timing Diagrams Read Cycle Timing [15] Note: 15. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW.
CY7C1324H Document #: 001-00208 Rev . *B Page 1 1 of 15 Write Cycle T iming [15, 16] Note: 16. Full width Write can be initiated b y either GW LOW; or by GW HIGH, BWE LOW and BW [A:B] LOW.
CY7C1324H Document #: 001-00208 Rev . *B Page 12 of 15 Read/Write T i ming [15, 17, 18] Notes: 17. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed.
CY7C1324H Document #: 001-00208 Rev . *B Page 13 of 15 ZZ Mode T iming [19, 20] Notes: 19. Device must be deselected when entering ZZ mode. See Cycle Descr iptions t able for all possible signal conditions to deselect the device. 20. DQs are in High-Z when exiting ZZ sleep mode.
CY7C1324H Document #: 001-00208 Rev . *B Page 14 of 15 © Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bj ect to ch ange without notice. Cypress S em ic on duct or Corpo ration assu mes no resp onsib ility for th e u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C1324H Document #: 001-00208 Rev . *B Page 15 of 15 Document History Page Document Title: CY7C1324H 2-Mbit (128K x 18) Flow-Throu gh Sync SRAM Document Number: 00 1-00208 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 347377 See ECN PCI New Data Sheet *A 428408 See ECN NXR Converted from Preliminary to Final.
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