Instruction/ maintenance manual of the product CY7C1307BV25 Cypress
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18-Mbit Burst of 4 Pipelined SRAM with Q DR™ Architecture CY7C1307BV25 CY7C1305BV25 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05630 Rev .
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 2 of 21 Selection Guide CY7C1305BV25-167 CY7C1307BV25-167 Unit Maximum Operating Freq uency 167 MHz Maximum Operating Current 400 mA 256Kx18 Array CLK A [17:0] Gen. K K Control Logic Address Register D [17:0] Read Add.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 3 of 21 Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm ) Pinout CY7C1305BV25 (1M x 18 ) 1 2 3 4 5 678 9 1 0 1 1 A NC GND/ 144M NC/ 36M .
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 4 of 21 Pin Definitions Name I/O Description D [x:0] Input- Synchronous Data input signals, sampled on the ris ing edge of K and K clocks during valid write operations . CY7C1305BV25 – D [17:0] CY7C1307BV25 – D [35:0] WPS Input- Synchronous Write Port Select, active LOW .
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 5 of 21 Introduction Functional Overview The CY7C1305BV25/CY7C1307BV25 are synchro nous pipelined Burst SRAMs equipp ed with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write Port is dedicated to Write operations.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 6 of 21 When deselected, the wr ite po rt will ign ore all i npu ts after the pending Write operations have been completed . Byte Write Operations Byte Write operations are supported by th e CY7C1305BV25.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 7 of 21 T ruth T able [2, 3, 4, 5, 6, 7, 8, 9] Operation K RPS WPS DQ DQ DQ DQ Write Cycle : Load address on the rising edge of K; wait one cycle; input write data on two consecutive K and K rising edges.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 8 of 21 Write Cycl e Descriptions (CY7C1307BV25) [2, 10 ] BWS 0 BWS 1 BWS 2 BWS 3 KK Comment s L L L L L-H – During the Data portion of a Write sequence, all four bytes (D [35:0] ) are written into the device.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 9 of 21 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial bo undary scan test access port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149 .
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 10 of 21 is loaded into the instruction register upon power-up or whenever the T AP controller is given a test logic reset state.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 1 1 of 21 T AP Controller St ate Diagram [1 1] Note: 1 1. The 0/1 next to each state re presents the value at TMS at th e rising edge of TCK.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 12 of 21 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating R ange [12, 15, 17] Parameter Description T est Conditions Min. Max. Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 13 of 21 Output Times t TDOV TCK Clock LOW to TDO V alid 20 ns t TDOX TCK Clock LOW to TDO Invalid 0 ns T AP Timing and T est Conditions [1.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 14 of 21 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Inpu t/Output ring contents.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 15 of 21 Boundary Scan Order Bit # Bum p ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11 H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 16 of 21 Maximum Ratings (Above which the useful life may be impaired.) S torage T e mperature .............. .................. –65°C to + 150°C Ambient T emperature with Power Applied .
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 17 of 21 Cap acit ance [22] Parameter Descript ion T es t Conditions Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 2.5V . V DDQ = 1.5V 5p F C CLK Clock Input Capacitance 6 pF C O Output Capacitance 7 pF AC T est Loads and W aveforms 1.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 18 of 21 Switching Characteristics Over the Operating Range [23] Cypress Parameter Consortium Parameter Description 167 MHz Unit Min. Max. t Power [24] V CC (typical) to the First Access Read or Write 10 µ s Cycle Time t CYC t KHKH K Clock and C Clock Cycle T ime 6.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 19 of 21 Switching W aveforms [27, 28, 29] Notes: 27. Q00 refers to output from address A0. Q01 refers to output from the ne xt internal burst address follo wing A0, i.e., A0+1. 28. Outputs are disabled (High- Z) one clock cycle after a NOP .
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 20 of 21 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce.
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 21 of 21 Document History Page Document Title: CY7C1305BV25/CY7C1307BV25 18 -Mb it Burst of Four Pipelined SRAM with QDR™ Architecture Document Number: 38-05630 REV . ECN NO. Issue Date Orig.
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