Instruction/ maintenance manual of the product CY7C1217H Cypress
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CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAM Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05670 Rev . *B Revised July 6, 2006 Features • 32K x 36 common I/O • 3.3V core power supply (V DD ) • 2.
CY7C1217H Document #: 38-05670 Rev . *B Page 2 of 16 Logic Block Diagram ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE .
CY7C1217H Document #: 38-05670 Rev . *B Page 3 of 16 Pin Configuration 100-Pin TQFP A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/9M A A A A A NC/4M DQP B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ.
CY7C1217H Document #: 38-05670 Rev . *B Page 4 of 16 Pin Descriptions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 32K address location s. Sampled at the rising edge of the CL K if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active.
CY7C1217H Document #: 38-05670 Rev . *B Page 5 of 16 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge o f the clock.
CY7C1217H Document #: 38-05670 Rev . *B Page 6 of 16 ZZ Mode Electrical Characteristics Parameter Description T est Conditions Min. Max. U nit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 40 mA t ZZS Device operation to ZZ ZZ > V DD – 0.
CY7C1217H Document #: 38-05670 Rev . *B Page 7 of 16 T ruth T able for Read/W rite [2, 3] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte (A, DQP A ) H L HHH L Write By.
CY7C1217H Document #: 38-05670 Rev . *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. ... ... ... ... ....... –65 ° C to + 150 ° C Ambient T e mperature with Power Applied .
CY7C1217H Document #: 38-05670 Rev . *B Page 9 of 16 Cap acit ance [9] Parameter Description T est Co nditions 100 TQFP Max. Unit C IN Input Capacit ance T A = 25 ° C, f = 1 MHz, V DD = 3.
CY7C1217H Document #: 38-05670 Rev . *B Page 10 of 16 Switching Characteristics Over the Operating Range [10, 1 1] Parameter Description 133 MHz 100 MHz Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the First Access [12] 11 m s Clock t CYC Clock Cycle T ime 7.
CY7C1217H Document #: 38-05670 Rev . *B Page 1 1 of 16 Timing Diagrams Read Cycle Timing [16] Note: 16. On this diagram, when CE is L OW, CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW.
CY7C1217H Document #: 38-05670 Rev . *B Page 12 of 16 Write Cycle T iming [16, 17] Note: 17. Full width Write can be initiated b y either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW.
CY7C1217H Document #: 38-05670 Rev . *B Page 13 of 16 Read/Write T iming [16, 18, 19] Notes: 18. The data bus (Q) remains in High-Z following a Write cycle unless an ADS P , ADSC , or ADV cycle is performed.
CY7C1217H Document #: 38-05670 Rev . *B Page 14 of 16 ZZ Mode T iming [20, 21] Notes: 20. Device must be deselected when ente ring ZZ mode. See Cycle Descr iptions t ab le for all possible signal conditi ons to deselect the device. 21. DQs are in High-Z when exiting ZZ sleep mode.
CY7C1217H Document #: 38-05670 Rev . *B Page 15 of 16 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C1217H Document #: 38-05670 Rev . *B Page 16 of 16 Document History Page Document Title: CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAM Document Number: 38 -05670 REV .
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