Instruction/ maintenance manual of the product CY7C1168V18 Cypress
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CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 18-Mbit DDR-II+ SRAM 2-W ord Burst Architecture (2.5 Cycle Read Latency) Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-06620 Rev .
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 2 of 27 Logic Block Diagram (CY7C1 166V18) Logic Block Diagram (CY7C1 177V18) CLK A (19:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 3 of 27 Logic Block Diagram (CY7C1 168V18) Logic Block Diagram (CY7C1 170V18) CLK A (18:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 4 of 27 Pin Configurations CY7C1 166V18 (2M x 8 ) 165-Ball FBGA (13 x 15 x 1.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 5 of 27 Pin Configurations (continued) CY7C1 168V18 (1M x 18) 165-Ball FBGA (13 x 15 x 1.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 6 of 27 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input Output- Synchronous Data Input Output Signal s . Inputs are sampled on the rising edge of K an d K clocks during valid write operations.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 7 of 27 ZQ Input Output Im pedance Matching I nput . This input is used to tune the device output s to the system data bus impedance. CQ, CQ, and Q [x:0] output impedance are set to 0.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 8 of 27 Functional Overview The CY7C1 166V18, CY7C1 1 77V18, CY7C1 168V18, and CY7C1 170V18 are syn chronous pipelined Burst SRAMs equipped with a DDR inte rface.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 9 of 27 echo clock and follows the ti ming of any data pin.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 10 of 27 Write Cycle Descriptions The write cycle descriptions of CY7C 1 166V18 and CY7C1 168V18 follows.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 1 1 of 27 The write cycle descriptions of CY7C1 170V18 follows.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 12 of 27 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan test access port (T AP) in the FBGA package. This part is fully comp liant with IEEE S t andard #1 149.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 13 of 27 IDCODE The IDCODE instruction causes a vendor-specific 32-bit code to be loaded into the instruction register .
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 14 of 27 T AP Controller St ate Diagram Figure 2 shows the tap controller state diagram.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 15 of 27 T AP Controller Blo ck Diagram Figure 3. T a p Controller Block Diagram T AP Electrical Characteristics The T ap Electrical Characteristics table over the operating range follows.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 16 of 27 T AP AC Switchi ng Characteristics The T ap AC Switching Characteristi cs over the operatin g range follows.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 17 of 27 Identification Regi ster Definitions Instruction Field Va l u e Description CY7C1 166V18 CY7C1 177V18 CY7C1 168V18 CY7C 1 170V18 Revision Number (31:29) 000 000 000 000 V ersion number .
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 18 of 27 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 1 1H 54 7B 8.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 19 of 27 Power Up Sequence in DDR-II+ SRAM DDR-II+ SRAMs must be powered up and initialize d in a predefined manner to prevent undefined opera tions. During power up, when the DOFF is tie d HIGH, the DLL gets locked after 2048 cycles of stable clock.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 20 of 27 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. User gui d el i ne s are not tested. S torage T emperature ..
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 21 of 27 Cap acit ance T ested initially and after any design or proc ess change that may affect these parameters. Parameter Descriptio n T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 22 of 27 Switching Characteristics Over the operating range [20, 21] Cypress Parameter Consortium Paramet.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 23 of 27 Switching W aveform Read/Write /Deselect Sequence Figure 7.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 24 of 27 Ordering Information Not all of the speed, package and temperature ranges are a v ailable. Contact your local sales representative or visit www .cypress.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 25 of 27 333 CY7C1 166V18 -333BZC 51-85180 165 -Ball Fi ne Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1 177V18-333BZC CY7C1 168V18-333BZC CY7C1 170V18-333BZC CY7C1 166V18-333BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
CY7C1 166V18, CY7C1 177V18 CY7C1 168V18, CY7C1 170V18 Document Number: 001-06620 Rev . *D Page 26 of 27 Package Diagram Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-8 5180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.
Document Number: 001-06620 Rev . *D Revised March 06, 2008 Page 27 of 27 QDR™ is a trademark of Cypress Semicond uctor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of prod ucts developed by Cypress, IDT , NEC, Renesas, and Samsung.
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