Instruction/ maintenance manual of the product CY7C027V Cypress
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CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V 3.3V 32K/64K x 16/18 Dual-Port S tatic RAM Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06078 Rev .
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 2 of 18 Pin Configurations Figure 1. 100-Pin TQ FP (T op V iew) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 3 of 18 Pin Configurations (continued) Figure 2. 100-Pin TQ FP (T op V iew) 1 3 2 92 91 90 84 85 87 86 88 89 83 8 2 8.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 4 of 18 Architecture The CY7C027V/027VN/027 A V/028V and CY7037V/037A V/038V consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O and addre ss lines, and control signals (C E , OE , R/W ).
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 5 of 18 generated to the owner . The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other p ort ’s mailbox without resetting the interrupt.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 6 of 18 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. User gui d elines are not teste d . S torage T emperature ............. ..
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 7 of 18 Figure 3. AC T est Loads and Waveforms 3.0V GND 90% 90% 10% 3n s 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load 1) R1 = 590 Ω 3.3V OUTPUT R2 = 435 Ω C= 3 0 pF V TH =1 .
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 8 of 18 Dat a Retention Mode The CY7C027V/027VN/027 A V/028V and CY7037V/037A V/038V are designed with b attery backup in mind. Data retention volt age and supply current are guaranteed over temper ature.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 9 of 18 Switching W aveforms Notes 15. R/W is HIGH for read cycles. 16. Device is continuously selected C E = V IL and UB or LB = V IL . This waveform cann ot be used for semaph ore reads.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 10 of 18 Notes 20. R/W mu st be HIGH during al l address transitio ns. 21. A write occurs during the overlap (t SCE or t PWE ) of a LOW CE or SEM and a LOW UB or LB . 22.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 1 1 of 18 Notes 29. CE = HIGH for the duration of the above timing (both write and re ad cycle). 30. I/O 0R = I/O 0L = LOW (request semaphore); CE R = CE L = HIGH. 31. Semaphores are reset (available to both ports) at cycle start.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 12 of 18 Note 33. CE L = CE R = LOW . Switching W aveforms (continued) VA L I D t DDD t WDD MA TCH MA TCH R/W R DA T A IN R DA T A OUTL t WC ADDRESS R t PWE VA L I D t SD t HD ADDRESS L t PS t BLA t BHA t BDD BUSY L Figure 1 1.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 13 of 18 Note 34. If t PS is violated, th e busy signal is asse rted on one side o r the other , but there is no g uarantee to which si de BUSY is asserted.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 14 of 18 Figure 15. Interrup t Timing Diagrams Notes 35. t HA depends on whi ch enable pi n (CE L or R/W L ) is deasserted first. 36. t INS or t INR depends on which en able pin (CE L or R/W L ) is asserted last.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 15 of 18 T able 1 . Non-Cont ending Read /Write Inputs Outpu ts CE R/W OE UB LB SEM I/O 9 – I/O 17 I/O 0 – I/O 8 .
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 16 of 18 Ordering Information 32K x16 3.3V Asynchron ous Dual-Port SRAM Spee d (ns) Orderin g Co de Pack age Name Pac.
CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V Document #: 38-06078 Rev . *B Page 17 of 18 Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Fla t Pac k (T QF P) A100 51-85048-*C [+] Feedb.
Document #: 38-06078 Rev . *B Revised December 09, 2008 Page 18 of 18 All products and c ompany names men tioned in th is document m ay be the tr ademarks o f t h eir respect i v e holders. CY7C027V/027VN/027A V/028V CY7C037V/037A V/038V © Cypress Semicondu ctor Corpor ation, 2001-200 8.
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