Instruction/ maintenance manual of the product AN6077 Cypress
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February 19, 2008 Document No. 001-15342 Rev . ** 1 with FX2LP Implementing an 8-Bit Asynchronous Interface Application Note Abstract This application note discusses how to configure the General Programmable Interface (GPIF) and slave FIFOs of the EZ-USB FX2LP™ to implement an 8-bit asynchronous interface.
February 19, 2008 Document No. 001-15342 Rev . ** 2 AN6077 GPIF Master Pin Descriptions The GPIF pin names, descriptions, an d their uses are dis- cussed in this section.
February 19, 2008 Document No. 001-15342 Rev . ** 3 AN6077 Figure 2 shows the GPIF De signer view of the FIFO Read waveform. FIFOWR When creating the F IFOWR waveform the following timin g parameters must be met.
February 19, 2008 Document No. 001-15342 Rev . ** 4 AN6077 Figure 4. FIFO Read Waveform in gpif.c Figure 5. FIFO Write W avefo rm in gpif.c 8051 Firmware Programming (Master) This section describes ho.
February 19, 2008 Document No. 001-15342 Rev . ** 5 AN6077 The firmware uses the AUTO mode for both IN and OUT transfers. Th is means that the maximum size (512 bytes) packets are committed automat ical ly from the pe ripheral domain to the USB domai n for OUT transfers.
February 19, 2008 Document No. 001-15342 Rev . ** 6 AN6077 IOA = 0x80; xFIFOTC_OUT = ( ( EP2FIFOBCH << 8 ) + EP2FIFOBCL ); // setup GPIF transaction count SYNCDELAY; EP2GPIFTCH = EP2FIFOBCH; SYN.
February 19, 2008 Document No. 001-15342 Rev . ** 7 AN6077 if( EP68FIFOFLGS & 0x01 ) { // EP6FF=1, when fifo "full" } else { // EP6FF=0, when fifo "not full", fo r example, buf.
February 19, 2008 Document No. 001-15342 Rev . ** 8 AN6077 Code Listing for Master Side #pragma NOIV // D o not generate interrupt vectors #include "fx2.
February 19, 2008 Document No. 001-15342 Rev . ** 9 AN6077 // EP4 and EP8 are not used in thi s implementation SYNCDELAY; // EP4CFG = 0x20; // c lear valid bit SYNCDELAY; // EP8CFG = 0x60; // c lear v.
February 19, 2008 Document No. 001-15342 Rev . ** 10 AN6077 } #define GPIFTRIGWR 0 #define GPIFTRIGRD 4 #define GPIF_EP2 0 #define GPIF_EP4 1 #define GPIF_EP6 2 #define GPIF_EP8 3 void TD_Poll( void ).
February 19, 2008 Document No. 001-15342 Rev . ** 1 1 AN6077 // setup GPIF transaction count SYNCDELAY; EP2GPIFTCH = EP2FIFOBCH; SYNCDELAY; EP2GPIFTCL = EP2FIFOBCL; // trigger FIFO write tran saction(.
February 19, 2008 Document No. 001-15342 Rev . ** 12 AN6077 // RDY0=1, when peripheral i s "not empty" // drive FIFOADDR lines OEA = 0xC0; IOA = 0x00; if( EP68FIFOFLGS & 0x01 ) { // EP6F.
February 19, 2008 Document No. 001-15342 Rev . ** 13 AN6077 } BOOL TD_Suspend( void ) { // Called before the device goes i nto suspend mode return( TRUE ); } BOOL TD_Resume( void ) { // Called after t.
February 19, 2008 Document No. 001-15342 Rev . ** 14 AN6077 { // Called when a Set Interface com mand is received EP0BUF[ 0 ] = AlternateSetting; EP0BCH = 0; EP0BCL = 1; return( TRUE ); // Handled by .
February 19, 2008 Document No. 001-15342 Rev . ** 15 AN6077 EZUSB_IRQ_CLEAR( ); USBIRQ = bmURES; // Clear U RES IRQ } void ISR_Susp( void ) interrupt 0 { Sleep = TRUE; EZUSB_IRQ_CLEAR( ); USBIRQ = bmS.
February 19, 2008 Document No. 001-15342 Rev . ** 16 AN6077 } void ISR_Ep1pingnak( void ) interrup t 0 { } void ISR_Ep2pingnak( void ) interrup t 0 { } void ISR_Ep4pingnak( void ) interrup t 0 { } voi.
February 19, 2008 Document No. 001-15342 Rev . ** 17 AN6077 } void ISR_Ep8fflag( void ) interrupt 0 { } void ISR_GpifComplete( void ) interr upt 0 { } void ISR_GpifWaveform( void ) interr upt 0 { // FIFORd WF detected peripheral prematurely empty (less than max .
February 19, 2008 Document No. 001-15342 Rev . ** 18 AN6077 // PINFLAGSxx EPxFIFOIRQ // EPxFIFOIE GPIFIRQ // GPIFIE GPIFADRH:L // UDMACRCH:L EPxGPIFTRIG // GPIFTRIG SYNCDELAY; FIFORESET = 0x80; // a ctivate NAK-ALL to avoid race co nditions SYNCDELAY; // s ee TRM section 15.
February 19, 2008 Document No. 001-15342 Rev . ** 19 AN6077 EP2FIFOCFG = 0x10; // A UTOOUT=1, WORDWIDE=0 SYNCDELAY; EP6FIFOCFG = 0x0C; // A UTOIN=1, ZEROLENIN=1, WORDWIDE=0 SYNCDELAY; } void TD_Poll( .
February 19, 2008 Document No. 001-15342 Rev . ** 20 AN6077 EP0BUF[ 0 ] = Configuration; EP0BCH = 0; EP0BCL = 1; return(TRUE); // Handled by user code } BOOL DR_SetInterface( void ) { // Called when a.
February 19, 2008 Document No. 001-15342 Rev . ** 21 AN6077 USBIRQ = bmSOF; // Clear S OF IRQ } void ISR_Ures( void ) interrupt 0 { if ( EZUSB_HIGHSPEED( ) ) { pConfigDscr = pHighSpeedConfig Dscr; pOt.
February 19, 2008 Document No. 001-15342 Rev . ** 22 AN6077 } void ISR_Ep4inout( void ) interrupt 0 { } void ISR_Ep6inout( void ) interrupt 0 { } void ISR_Ep8inout( void ) interrupt 0 { } void ISR_Ibn.
AN6077 Cypress Semico nd uctor 198 Champi on Cou rt San Jose, CA 9513 4-1709 Phone: 408- 943-2600 Fax: 408-94 3-4730 http://www.cypr ess.com © Cypress S emiconducto r Corpora tion, 200 6-2008. The informati on contained herein is subject to chang e without notice.
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