Instruction/ maintenance manual of the product L5630 Intel
Go to page of 46
Reference Number:323372-001 Intel® Xeon® Processor 5600 Series Specification Update March 2010.
2 Intel® Xeon® Processor 5600 Series Specification Update, March 2010 Legal Lines and Disclaime rs INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNE CTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRE SS OR IMPLIED, BY ESTOPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT .
Intel® Xeon® Processor 5600 Series 3 Specification Update, March 2010 Contents Revision History ................ ............ ................. ............. ................ ............. ................ ........ 5 Preface .............. .........
Intel® Xeon® Processor 5600 Series 4 Specification Update, March 2010.
Intel® Xeon® Processor 5600 Series 5 Specification Update, March 2010 Revision History Doc ID Revision Description Date 323372 -001 • Initial R elease March 2010.
Intel® Xeon® Processor 5600 Series 6 Specification Update, March 2010 Preface This document is an update to th e specifications contained in the Affected Documents able below . This document is a compilation of device and documentation errata, specification clarifications and changes.
Intel® Xeon® Processor 5600 Series 7 Specification Update, March 2010 Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g. , core speed, L2 cache size, package type, etc.
Intel® Xeon® Processor 5600 Series 8 Specification Update, March 2010 Identification Information Component Identification The Intel® X eon® Processor 5600 Series stepping can be ide ntified by the following register contents.
Intel® Xeon® Processor 5600 Series 9 Specification Update, March 2010 Component Marking The Intel® X eon® Processor 5600 Series can be identified by the following component markings: Figure 1.
Intel® Xeon® Processor 5600 Series 10 Specification Update, March 2010 Notes: 1. CPUID is 0000206Csh, where ‘s’ is the stepping number . 2. This is an Intel® Xe on Processor X5680. 3. This is an Intel® Xe on Processor X5677. 4. This is an Intel® Xe on Processor X5670.
Intel® Xeon® Processor 5600 Series 11 Specification Update, March 2010 Summary Table of Changes The table included in this section indi cate the err ata, Specification Changes, Specification Clarifications, or Document Changes which apply to the Intel® X eon® Processor 5600 Series.
Intel® Xeon® Processor 5600 Series 12 Specification Update, March 2010 T = Mobile Intel® Pentium® 4 processor-M U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache V = Mobile Intel® Celeron® processor on .
Intel® Xeon® Processor 5600 Series 13 Specification Update, March 2010 AAB= Intel® X eon® E3110 processor AAC= Intel® Celeron® dual-core processor E1000 series AAD = Intel ® Core™2 Extreme pr.
Intel® Xeon® Processor 5600 Series 14 Specification Update, March 2010 Errata Summary Table 3. Errata Summary Table (Sheet 1 of 4) Errata Number Steppings Status ERRATA B-1 BD1 X No Fix The Processo.
Intel® Xeon® Processor 5600 Series 15 Specification Update, March 2010 BD25 X No Fix Intel® QuickPath Memory Controller May Hang Due to Uncorrectable ECC Erro rs Occurring on Both Channels in Mirro.
Intel® Xeon® Processor 5600 Series 16 Specification Update, March 2010 BD52 X No Fix Memory Aliasing of Code Pages May Cause Unpredictable System Behavior BD53 X No Fix Performance Monitor Counters .
Intel® Xeon® Processor 5600 Series 17 Specification Update, March 2010 BD79 X No Fix APIC T imer CCR May Report 0 in Periodic Mode BD80 X No Fix LBR, BTM or BTS Records May have In correct Branch Fr.
Intel® Xeon® Processor 5600 Series 18 Specification Update, March 2010 Errata BD1. The Processor may Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (T ask -State Segment) may cause a #TS (invalid T SS exception) instead of a #GP f ault (general p rotection exception).
Intel® Xeon® Processor 5600 Series 19 Specification Update, March 2010 W orkaround: None identified. Status: For the steppin gs affected, see the Summary Table of Changes .
Intel® Xeon® Processor 5600 Series 20 Specification Update, March 2010 did occur in V86 mode, the exception may be directed to the gener al-protection exception handler .
Intel® Xeon® Processor 5600 Series 21 Specification Update, March 2010 Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture , for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3.
Intel® Xeon® Processor 5600 Series 22 Specification Update, March 2010 during a specific boundary condition where the exception/interrupt occurs right after the execution of an instruction at th e l.
Intel® Xeon® Processor 5600 Series 23 Specification Update, March 2010 Management Mode) may cause the lower two bits of CS segment register to be corrupted.
Intel® Xeon® Processor 5600 Series 24 Specification Update, March 2010 BD22. Improper Parity Error Signaled in the IQ Follo wing Reset When a Code Breakpoint is Set on a #GP Instruction Problem: Whi.
Intel® Xeon® Processor 5600 Series 25 Specification Update, March 2010 BD25. Intel® QuickPath Memory Contro ller May Hang Due to Uncorrectable ECC Errors Occurring on B oth Ch annels in Mirror Chan.
Intel® Xeon® Processor 5600 Series 26 Specification Update, March 2010 BD29. Disabling Thermal Monitor While Pr ocessor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Problem: If.
Intel® Xeon® Processor 5600 Series 27 Specification Update, March 2010 BD32. xAPIC Timer May Decremen t To o Quickly Following an Automatic Reload While in Periodic Mode Problem: When the xAPIC Timer is automat ically reload ed by counting down to zero in periodic mode, the xAPIC Timer may slip in its sync hronization with the external clock.
Intel® Xeon® Processor 5600 Series 28 Specification Update, March 2010 W orkaround: As long as machine check exceptions are enabled, the machine check exception handler can log the TLB error prior to core C6 entry . This will ensure the error is logged before it is cleared.
Intel® Xeon® Processor 5600 Series 29 Specification Update, March 2010 be processed after C6 wakeup and after interrupts are re-enabled (EFLAGS.IF=1). However , the pending interrupt event will not be cleared. Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the external interrupt.
Intel® Xeon® Processor 5600 Series 30 Specification Update, March 2010 Status: For the steppin gs affected, see the Summary Table of Changes . BD42. APIC Error “Received Illegal Vector” May be L.
Intel® Xeon® Processor 5600 Series 31 Specification Update, March 2010 BD46. ECC Errors Can Not be Injected on Back-to-Back Writes Problem: E C C e r r o r s s h o u l d b e i n j e c t e d o n e v e r y write that matches the address set in the MC_CHANNEL_{0,1,2}_AD DR_MA TCH CSRs.
Intel® Xeon® Processor 5600 Series 32 Specification Update, March 2010 BD50. Failing DIMM ID May be Incorrect in the 2DPC Configuration When Mirroring is Enabled Problem: When redundancy is lost in .
Intel® Xeon® Processor 5600 Series 33 Specification Update, March 2010 registers, then programming three event v alues 0x4300D2, 0 x4300B1 and 0x4300B5 into the IA32_PERFEVTSELx MSRs, and fina lly continuing with new event programming and restoring previous programming if necessary .
Intel® Xeon® Processor 5600 Series 34 Specification Update, March 2010 EFLAGS Discrepancy on Page Faults an d on EPT-Induced VM Ex its after a Translation Change Problem: This err atum is regardin g.
Intel® Xeon® Processor 5600 Series 35 Specification Update, March 2010 ASR_PRESENT was intended to allow low power self refresh with DRAM that does not support automatic self refresh. W orkaround: It is possible for Intel prov ided BIOS reference code to contain a workaround for this erratum.
Intel® Xeon® Processor 5600 Series 36 Specification Update, March 2010 of load or store instructions retired. However , due to this erratum, they may underco unt. Implication: The performance monitor event INSTR_RETI RED and MEM_INST_RET IRED may reflect a count lower than the actual number of events.
Intel® Xeon® Processor 5600 Series 37 Specification Update, March 2010 BD66. Pending x8 7 FPU Exceptions (# MF) May be Signaled Earlier Than Expected Problem: x87 instructions that trigger #MF normally service interrupts before the #MF .
Intel® Xeon® Processor 5600 Series 38 Specification Update, March 2010 overly aggressive in demoting OS C -sate re quests to a C-sate with higher power and lower exit latency . Implication: This aggressive demotion can result in higher platform power under idle conditions.
Intel® Xeon® Processor 5600 Series 39 Specification Update, March 2010 BD73. Performance Moni toring Events STORE_BLOCKS.NOT_STA an d STORE_BLOCKS.STA May No t Count Events Correctly Problem: P erformance Monitor Events STORE_BL OCKS.NO T_ST A and ST ORE_BLOCKS.
Intel® Xeon® Processor 5600 Series 40 Specification Update, March 2010 determines this asserted state as another PECI host initiating a transaction, it ma y release control of the bus resulting in a permanent tri-state condition.
Intel® Xeon® Processor 5600 Series 41 Specification Update, March 2010 BD80. PEBS Records Not Crea ted For FP-Assists Events Problem: When a performance monitor counter is configured to count FP_ASSIST S (Event: F7H) and to trigger PEBS (Precise Ev ent Based Sa mpling), the processor does not create a PEBS record when the counter ov erflows.
Intel® Xeon® Processor 5600 Series 42 Specification Update, March 2010 BD84. PECI Reads of Machine Ch eck MS Rs in the Processor Core May Not Function Correctly Problem: PECI reads which target machine check MSRs in the processor core may either be directed to a different core than intended or report that the data is not a vailable.
Intel® Xeon® Processor 5600 Series 43 Specification Update, March 2010 BD88. FP Data Operand Poin ter May Be Incorrectly Calculated After an FP Access Which Wraps a 64-Kbyte Boundary in 16-bit Code .
Intel® Xeon® Processor 5600 Series 44 Specification Update, March 2010 Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Xeon® Pro.
Intel® Xeon® Processor 5600 Series 45 Specification Update, March 2010 Specification Clarifications The Specification Changes listed in this section apply to the following documents: • Intel® Xeo.
Intel® Xeon® Processor 5600 Series 46 Specification Update, March 2010 Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Xeon® Pro.
An important point after buying a device Intel L5630 (or even before the purchase) is to read its user manual. We should do this for several simple reasons:
If you have not bought Intel L5630 yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data Intel L5630 - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, Intel L5630 you will learn all the available features of the product, as well as information on its operation. The information that you get Intel L5630 will certainly help you make a decision on the purchase.
If you already are a holder of Intel L5630, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Intel L5630.
However, one of the most important roles played by the user manual is to help in solving problems with Intel L5630. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device Intel L5630 along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
